Descripción de la oferta
You will own the thermal path from die junction to facility water — on-die hotspots, package spreading, cold plate design, sled airflow and rack-level heat rejection. Senior IC role: you set the thermal budget the rest of the hardware team designs against.What you will work on:Thermal solution for a multi-die AI accelerator at high TDPLiquid cooling: cold plate, manifold, loop design and facility interfaceDie-level hotspot and transient thermal analysis using power mapsSled, shelf and rack thermal architecture, including hybrid air and liquidThermal telemetry, throttling policy and thermal-aware power managementResponsibilities:Analysis & modelling: Build detailed and compact thermal models of die, package and board. Run CFD and conjugate heat transfer studies for cold plate, sled and rack. Perform transient analysis against real workload power profiles, not just steady-state TDP.Solution design: Specify cold plate geometry, flow rate, pressure drop and TIM stack. Define thermal interface requirements and bond line targets, and own the junction temperature budget across all rails and dies.System & rack: Define flow distribution, coolant temperature and approach, redundancy behaviour and failure response. Set the thermal design envelope for the sled and the rack it sits in.Validation & cross-functional: Own thermal validation on real silicon — instrumentation, on-die sensor correlation, flow and pressure measurement. Partner with mechanical on mounting and load, with power on throttling policy, and with cooling vendors on components and qualification.Requirements:8+ years in electronics thermal engineering for high-power computing, datacentre or comparable systemsProven thermal ownership of a processor, GPU, ASIC or FPGA at high TDP, including package-level analysisStrong CFD and thermal simulation experience — Icepak, Flotherm, Star-CCM+ or equivalentLiquid cooling design experience: cold plates, flow and pressure budgets, loop behaviourWorking knowledge of TIM selection, bond line control and thermal interface reliabilityHands-on thermal validation and model-to-measurement correlationNice to Have:2.5D, interposer or chiplet package thermal co-designTwo-phase, immersion or direct-to-chip cooling experienceOCP rack cooling standards, ORv3, or facility water interface designElectro-thermal co-simulation with power delivery and PDN teamsPython for automation, model generation andtest data analysisWhy Semidynamics?Work for one of Europe’s most promising deep-tech semiconductor scale-ups.Accelerated development path.4 days per week in the Barcelona office (city center), 1 day WFH.1 week of work from everywhere in the world.Competitive package.A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.#J-18808-Ljbffr
