Descripción de la oferta
About the Company At LuxQuanta, we are pioneering the Quantum Communications industry by delivering solutions that use the properties of quantum physics to secure communications. As we spearhead our international expansion after our first three years of solid growth, we invite passionate individuals to join us on our journey. We expect you to help us continue leading the fast-paced market of Quantum Communications in Europe and beyond. About the role The ideal candidate will be responsible for maintaining the RTL codebase and low-level Python/Rust firmware, as well as taking ownership of CI/CD pipelines for testing, synthesis, and implementation. He/she will gain deep knowledge of the underlying DSP and gateware/firmware interfaces and will eventually take responsibility for the continuous improvement of the FPGA logic that orchestrates our commercial CV-QKD products. Tasks & Responsibilities Understand the DSP and RTL architecture of the CV-QKD transceiver Design and maintain CI/CD pipelines for RTL unit testing, system-level testing, and bitstream generation Collaborate with the firmware team to strengthen the security and resilience of Python and Rust drivers Support the production and testing teams in identifying and resolving bottlenecks and failures for upcoming FPGA image and driver releases Assist the production and testing teams in evaluating and integrating new opto-electronic components Perform hands-on testing and verification on dedicated CV-QKD transceivers at LuxQuanta’s facilities, when required Qualifications / Experience : Degree in Electronics Engineering, Electrical Engineering, Physics, Telecommunications, or a related field 4+ years of experience in FPGA programming in an industrial or production environment Programming languages: Verilog, Python, C, TCL (Rust is a plus) Proficiency in developing and testing RTL code for AMD/Xilinx FPGAs, including AXI-4 interfaces, IP packaging flows, and timing closure analysis Experience developing low-level driver code (Python, C, or Rust) to control RTL logic and external peripherals via SPI/I2C Experience designing and maintaining CI/CD pipelines and using external testing/build agents for RTL testing and bitstream generation Proficient with Git and standard version control workflows Basic electronics knowledge, including the ability to read schematics and datasheets Strong collaboration skills and the ability to work closely with firmware and hardware engineers during system design Experience with Zynq / Zynq UltraScale+ FPGA architectures is a plus Experience with embedded build environments (e.g., Buildroot, Yocto, Petalinux) is a plus Compensation Competitive salary, private health insurance and ticket guarderia. Lunch at the office for less than 2€! Flexible working hours and hybrid work model. Short Fridays during the Summer. Opportunities for professional development and career growth in a vibrant multicultural work environment in Barcelona.
